9 research outputs found
Crosstalk computing: circuit techniques, implementation and potential applications
Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model.
Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style.
Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Crosstalk computing, involving engineered interference between nanoscale
metal lines, offers a fresh perspective to scaling through co-existence with
CMOS. Through capacitive manipulations and innovative circuit style, not only
primitive gates can be implemented, but custom logic cells such as an Adder,
Subtractor can be implemented with huge gains. Our simulations show over 5x
density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper
introduces the Crosstalk circuit style and a key method for large-scale circuit
synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS
synthesis flow by adding two extra steps: conversion of the gate-level netlist
to Crosstalk implementation friendly netlist through logic simplification and
Crosstalk gate mapping, and the inclusion of custom cell libraries for
automated placement and layout. Our logic simplification approach first
converts Cadence generated structured netlist to Boolean expressions and then
uses the majority synthesis tool to obtain majority functions, which is further
used to simplify functions for Crosstalk friendly implementations. We compare
our approach of logic simplification to that of CMOS and majority logic-based
approaches. Crosstalk circuits share some similarities to majority synthesis
that are typically applied to Quantum Cellular Automata technology. However,
our investigation shows that by closely following Crosstalk's core circuit
styles, most benefits can be achieved. In the best case, our approach shows 36%
density improvements over majority synthesis for MCNC benchmark
Thermal Management in Fine-Grained 3-D Integrated Circuits
For beyond 2-D CMOS logic, various 3-D integration approaches specially
transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2],
SN3D [3] holds most promise. However, such 3D architectures within small form
factor increase hotspots and demand careful consideration of thermal management
at all levels of integration [4] as stacked transistors are detached from the
substrate (i.e., heat sink). Traditional system level approaches such as liquid
cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D
integration and have huge cost overhead [7]. In this paper, we investigate the
thermal profile for transistor level 3-D integration approaches through finite
element based modeling. Additionally, we propose generic physical level heat
management features for such transistor level 3-D integration and show their
application through detailed thermal modeling and simulations. These features
include a thermal junction and heat conducting nano pillar. The heat junction
is a specialized junction to extract heat from a selected region in 3-D; it
allows heat conduction without interference with the electrical activities of
the circuit. In conjunction with the junction, our proposed thermal pillars
enable heat dissipation through the substrate; these pillars are analogous to
TSVs/Vias, but carry only heat. Such structures are generic and is applicable
to any transistor level 3-D integration approaches. We perform 3-D finite
element based analysis to capture both static and transient thermal behaviors
of 3-D circuits, and show the effectiveness of heat management features. Our
simulation results show that without any heat extraction feature, temperature
for 3-D integrated circuits increased by almost 100K-200K. However, proposed
heat extraction feature is very effective in heat management, reducing
temperature from heated area by up to 53%.Comment: 9 Page